1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to, a negative word line driver in a semiconductor memory device.
2. Discussion of Related Art
The negative word line driver supplies VPP to a word line when enabling the word line, while supplying a voltage (hereinafter, denoted with VBBW) lower than VSS to a word line when disabling the word line.
As using this negative word line driving method, a refresh characteristic is improved as well as other AC parameters are. Especially, it increases a refresh time and decreases a VPP burden while using a low Vcc. Moreover, the negative word line driving method is employed in order to improve a write recovery time TWR.
It will be described about a negative word line driving method of conventional art in FIG. 1 with reference to FIGS. 1 to 4.
Referring to FIG. 1, a block select address Bax having a block information is generated from a select address generation unit 10 according to an active signal. As a main word line driver 40 is driven by block select addresses Bax3–12, a main word line mwl is selected. On the other hand, a phi X driver 30 is driven by block select addresses Bax0, 1, 2, and a sub word line driver 50 is driven by outputs fx, fxb of the phi X driver 30, to select a sub word line swl.
A row decoder controller 20 generates a precharge signal Xpcg for disabling a word line. The precharge signal Xpcg controls the phi X driver 30 and the main word line 40. That is, enabling a word line is performed in response to the block select address Bax, while disabling a word line is performed in response to the precharge signal Xpcg.
FIG. 2 is a detailed circuit diagram illustrating a row decoder controller of FIG. 1.
A NAND gate G1 combines a reverse signal of a signal R2ACB deciding a precharging timing and a block select enable signal BS, and then the output signal of the NAND gate G1 passes through inverters I1 to I3. Accordingly, an output of the inverter I3 becomes the precharge signal Xpcg.
FIG. 3 is a detailed circuit diagram illustrating a main word line driver of FIG. 1.
Signals Bax34<0:3> which have predecoded a block select address Bax34 are applied to gates of NMOS transistors Q1, Q2, Q3, Q4 and each source of the NMOS transistors Q1, Q2, Q3, Q4 is connected to a common node com.
One of signals Bax56<0:3> which have predecoded a block select address Bax56 is applied to a gate of NMOS transistor Q9 and one of signals Bax78<0:3> which have predecoded a block select address Bax78 is applied to a gate of NMOS transistor Q10. As a result, the NMOS transistors Q9, Q10 are turned on or off thereto. In condition that the NMOS transistors Q9, Q10 are turned on, When the NMOS transistor Q1 is turned on according to the predecoded signal Bax34<0>, a potential of node N1 becomes VBBW level. As the same to it, when the NMOS transistor Q2 is turned on according to the predecoded signal Bax34<1>, a potential of node N2 becomes VBBW level. When the NMOS transistor Q3 is turned on according to the predecoded signal Bax34<2>, a potential of node N3 becomes VBBW level. Additionally, when the NMOS transistor Q4 is turned on according to the predecoded signal Bax34<3>, a potential of node N4 becomes VBBW level.
On the other hand, when the precharge signal Xpcg is enabled, a signal predecoding a block select address is disabled, which results in that the NMOS transistors Q1 to Q4 are turned off and PMOS transistors Q5, Q6, Q7, Q8 are turned on. Accordingly, the nodes N1, N2, N3, N4 become high level.
The level of node N1 is shifted to VPP or VBBW level according to a low level shifter 40a, the level of node N2 is shifted to VPP or VBBW level according to a low level shifter 40b, and the level of node N3 is shifted to VPP or VBBW level according to a low level shifter 40c. Furthermore, the level of node N4 is shifted to VPP or VBBW level according to a low level shifter 40d. 
Each output of each low level shifter 40a 40d is inverted by corresponding inverter I4 to I7. A first main word line mwl<0> is driven or precharged in response to an output of the inverter I4. A second main word line mwl<1> is driven or precharged in response to an output of the inverter 15. A third main word line mwl<2> is driven or precharged in response to an output of the inverter 16. A fourth main word line mwl<3> is driven or precharged in response to an output of the inverter I7.
FIG. 4 is a detailed circuit diagram illustrating the level shifter of FIG. 3.
Because a PMOS transistor Q13 is turned on, when an input signal IN, namely, each node N1 to N4 of FIG. 3, is high level, a PMOS transistor Q11 and a NMOS transistor Q15 are turned on. As a result, the level shifter of FIG. 4 outputs VBBW. On the other hand, when the input signal IN is low level, a NMOS transistor Q14 and a PMOS transistor Q12 are turned on. As a result, the level shifter of FIG. 4 outputs VPP.
In the aforementioned conventional art, in order to precharge each main word line, that is, to become VBBW level, level shifters are connected to each main word line as shown in FIG. 3.
For instance, when each memory block uses 512 numbers of word lines and a phi X driver is coded by 4:1, 128 numbers of main word lines are required, and thus 128 numbers of level shifters should be connected to each main word line. Although the phi X driver is coded by 8:1, 64 numbers of main word lines are required, and thus the number of level shifters also needs as same as the number of main word lines.
Therefore, it causes problems that a chip size is increased and a signal for precharing a word line is delayed.